Semiconductor devices are widely used throughout the electronics industry. One factor driving their use is the ability to put more and more circuits on a silicon chip. For example, semiconductor memory manufacturers have steadily progressed from memories of the 16K type as shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine, to memories of the 1M type, as described in U.S. Pat. No. 4,658,377 issued to McElroy. Memories of the 4M type are now being produced, production plans for high density 16M memories having submicron technology now exist, and experimentation of 64M memories has begun. Other VLSI devices such as microprocessors are now produced that have more than one million transistors on chip.
In order to put more and more circuits on a silicon chip, without unduly increasing the size of the semiconductor chip, it is necessary to reduce the size of the individual semiconductor devices formed on the semiconductor chip. U.S. Pat. No. 4,240,092 to Kuo and U.S. Pat. No. 4,721,987 to Baglee et al, discuss scaling down the size of memory devices. U.S. Pat. No. 4,356,623 to Hunter, incorporated herein by reference, discusses scaling down the size of semiconductor transistors. Some encountered problems include parasitic capacitances, resistances, and punchthrough currents. Hunter's solution provides a Metal-Oxide-Semiconductor, MOS, transistor with a gate conductor within the range of about 0.1 microns to about 1 micron. A gate insulator is formed on top of a substrate and a gate conductor is formed on top of the gate insulator. The gate conductor has sidewall insulators. Ion implantation and subsequent drive-in anneal form the source/drain regions of the transistor. The source/drain regions extend underneath the sidewall insulators and underneath gate of the transistor.
Additional scaling of semiconductor devices is needed. By forming larger numbers of semiconductor devices in a semiconductor chip, the cost per device is greatly reduced. By increasing the density of semiconductor elements on a chip, the manufacturing costs can be decreased. This will allow further use and application of semiconductor devices throughout the electronics industry and benefit consumers.
The channel length scaling in MOS transistors is limited by the punchthrough voltage, i.e., the source to drain bias that produces current between the source and drain when the gate to source bias is at the "off" condition. The implanted source/drain regions to the typical planar self-aligned MOS transistor cannot be guaranteed to have a vertical doping profile before diffusion such that the highest doping concentration is at the silicon surface. Thus later diffusion, proportional to the concentration gradients, may be greater at some depth below the surface that is not adequately controlled by the gate. Very shallow voltage threshold, Vt, implants which counterdope the surface can contribute to this effect which results in sub-surface conduction at a source to drain voltage lower than that needed to produce current in the gate controlled surface channel at "off" bias.
It is an object of this invention to provide a method of manufacturing such small semiconductor device.
It is an additional object of this invention to arrange the surface channel and the source/drain diffusions such as to prevent the possibility of higher dopant concentrations in the substrate below the plane of the gate controlled channel, thereby preventing the sub-surface punchthrough and resulting lowering of the device punchthrough voltage.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification and drawings.